DocumentCode :
1278463
Title :
Property-based test generation for scan designs and the effects of the test application scheme and scan selection on the number of detectable faults
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Volume :
21
Issue :
5
fYear :
2002
fDate :
5/1/2002 12:00:00 AM
Firstpage :
628
Lastpage :
637
Abstract :
Scan circuits are considered under a test application scheme where a test consists of one or more primary input vectors embedded between a scan-in operation and a scan-out operation. The first property-based (simulation-based) test generation procedure under this test application scheme is described. The proposed procedure constructs tests that traverse as many pairs of fault-free/faulty states as possible. Additional techniques are incorporated into this basic procedure to enhance its effectiveness. Also considered for the first time is the set of detectable faults under this test application scheme. It is shown that it is a subset of the set of detectable faults obtained under the test application scheme where scan is applied with every primary input vector. It is also shown that the set of detectable faults depends strongly on the set of scanned flip-flops even when the percentage of scanned flip-flops is very high. This dependence at high levels of scan is significantly weaker when scan is applied with every primary input vector
Keywords :
automatic test pattern generation; circuit simulation; fault location; integrated circuit testing; integrated logic circuits; logic simulation; logic testing; detectable faults; fault-free/faulty state pairs; primary input vector scan application; primary input vectors; property-based test generation; scan circuits; scan designs; scan levels; scan selection; scan-in operation; scan-out operation; scanned flip-flops; simulation-based test generation procedure; test application scheme; Circuit faults; Circuit simulation; Circuit testing; Electrical fault detection; Fault detection; Logic circuits; Logic testing; Sequential analysis; Sequential circuits; Synchronous generators;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.998633
Filename :
998633
Link To Document :
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