Title :
Self-aligned offset gated poly-Si TFTs with a floating sub-gate
Author :
Park, Cheol-Min ; Min, Byung-Hyuk ; Jun, Jae-Hong ; Yoo, Juhn-Suk ; Han, Min-Koo
Author_Institution :
Sch. of Electr. Eng., Seoul Nat. Univ., South Korea
Abstract :
We have fabricated a self-aligned offset-gated poly-Si thin film transistor (TFT) by employing a novel photoresist reflow process. The gate structure of the new device is consisted of two unique patterns: A main-gate and a sub-gate. The new fabrication method extends the gate-oxide over the offset region. With the assistance of the sub-gate and reflowed photoresist a self-aligned offset region is successfully obtained due to the offset oxide acting as an implantation mask. The poly-Si TFT with symmetrical offsets is easily fabricated and the new method does not require any additional offset mask step. Compared with the misaligned offset gated poly-Si TFTs, excellent symmetric electrical characteristics are obtained.
Keywords :
elemental semiconductors; oxidation; photoresists; semiconductor technology; silicon; thin film transistors; I-V characteristics; Si-SiO/sub 2/; floating sub-gate; gate structure; implantation mask; off current ratio; offset oxide; photoresist reflow process; self-aligned offset gated poly-Si TFT; symmetric electrical characteristics; symmetrical offsets; Active matrix liquid crystal displays; Amorphous silicon; Electric variables; Electrodes; Fabrication; Leakage current; Resists; Semiconductor films; Stress; Thin film transistors;
Journal_Title :
Electron Device Letters, IEEE
