VLSI design for high-speed LZ-based data compression

A simple real-time parallel architecture for a CMOS VLSI implementation of a Ziv-Lempel data compression system is presented. This encoding system employs a linear systolic array to find concurrently the matches between each input data character and its corresponding dictionary, and can easily achieve an ideal compression ratio by cascading the chips of the encoding cell. A new encoding architecture is proposed to improve the encoding speed and reduce hardware complexity for the encoding cells. In addition, the number of memory accesses is reduced to save power consumption for high-speed applications. The encoder codes one character (more than eight bits) per encoding cycle. The clock rate by Verilog simulator can be constrained below 15 ns using the Compass standard cell library for the 0.6 μm CMOS process