Effects of floating-gate interference on NAND flash memory cell operation

Author

Jae-Duk Lee ; Sung-Hoi Hur ; Jung-Dal Choi

Author_Institution

Semicond. Res. & Dev. Center, Samsung Electron. Co. Ltd., Gyunggi, South Korea

Volume

23

Issue

5

fYear

2002

fDate

5/1/2002 12:00:00 AM

Firstpage

264

Lastpage

266

Abstract

Introduced the concept of floating-gate interference in flash memory cells for the first time. The floating-gate interference causes V_T shift of a cell proportional to the V_T change of the adjacent cells. It results from capacitive coupling via parasitic capacitors around the floating gate. The coupling ratio defined in the previous works should be modified to include the floating-gate interference. In a 0.12-μm design-rule NAND flash cell, the floating-gate interference corresponds to about 0.2 V shift in multilevel cell operation. Furthermore, the adjacent word-line voltages affect the programming speed via parasitic capacitors.

Keywords

MOS memory circuits; NAND circuits; cellular arrays; flash memories; integrated circuit modelling; multivalued logic; 0.12 micron; NAND flash memory cell; adjacent cells; adjacent word-line voltages; capacitive coupling; coupling ratio; floating-gate interference; multilevel cell operation; parasitic capacitors; programming speed; Flash memory cells; Integrated circuit modeling; Interference; MOS capacitors; Nonvolatile memory; Parasitic capacitance; Silicon; Thickness control; Threshold voltage; Voltage control;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.998871

Filename

998871