Hole tunneling current through oxynitride/oxide stack and the stack optimization for p-MOSFETs

Author

Yu, H.Y. ; Hou, Y.T. ; Li, M.-F. ; Kwong, D.L.

Author_Institution

Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore

Volume

23

Issue

5

fYear

2002

fDate

5/1/2002 12:00:00 AM

Firstpage

285

Lastpage

287

Abstract

A systematic study on hole-tunneling current through both oxynitride and oxynitride/oxide (N/O) stack is for the first time presented based on a physical model. The calculations are in good agreement with the available experimental data. With a given equivalent oxide thickness (EOT), and under typical operating gate voltages (|Vg|<2 V), hole-tunneling current (essentially the gate current) is found to be lowest through the oxynitride or N/O stack with /spl sim/33% of nitrogen (N). An optimized N/O stack structure with 33% (atomic percentage) nitrogen and with a 3 /spl Aring/ oxide layer for keeping acceptable channel interface quality is proposed to project the N/O gate dielectrics scaling limit using in MOSFETs.

Keywords

MOSFET; dielectric thin films; hole mobility; semiconductor device models; semiconductor device reliability; tunnelling; 3 angstrom; acceptable channel interface quality; dielectric films; equivalent oxide thickness; gate dielectrics scaling limit; hole tunneling current; operating gate voltages; oxynitride/oxide stack; p-MOSFETs; physical model; stack optimization; CMOS process; CMOS technology; Charge carrier processes; Dielectric materials; Gate leakage; MOSFET circuits; Nitrogen; Silicon; Tunneling; Voltage;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.998878

Filename

998878