A 0.25-μm CMOS 0.9-V 100-MHz DSP core

Author

Izumikawa, Masanori ; Igura, Hiroyuki ; Furuta, Koichiro ; Ito, Hiroshi ; Wakabayashi, Hitoshi ; Nakajima, Ken ; Mogami, Tohru ; Horiuchi, Tadahiko ; Yamashina, Masakazu

Author_Institution

Microelectron. Res. Labs., NEC Corp., Kanagawa, Japan

Volume

32

Issue

1

fYear

1997

fDate

1/1/1997 12:00:00 AM

Firstpage

52

Lastpage

61

Abstract

This paper describes a 0.25-μm CMOS 0.9-V 100-MHz DSP core which is composed of a 2-mW 16-b multiplier-accumulator and a 1.5-mW 8-kb SRAM. High-speed operation with a supply of less than 1 V has been achieved by developing 0.25-μm CMOS technology, reducing threshold voltage to 0.3 V, developing tristate inverter 3-2/4-2 adders for the multiplier, realizing small bit-line swing operation for the SRAM, and so on. The adder circuits operate faster than conventional adders at low supply voltages. In addition, short-circuit current and area for diffusion contact are reduced. Small bit-line swing operation has been realized by using a device-deviation immune sense amplifier. Leakage current during sleep mode was reduced by the use of high threshold voltage MOSFETs

Keywords

CMOS digital integrated circuits; adders; digital signal processing chips; leakage currents; multiplying circuits; random-access storage; 0.25 micron; 0.9 V; 1.5 mW; 100 MHz; 2 mW; CMOS; DSP core; SRAM; adders; bit-line swing operation; device-deviation immune sense amplifier; diffusion contact; high-speed operation; leakage current; multiplier-accumulator; short-circuit current; sleep mode; threshold voltage; tristate inverter; Adders; CMOS technology; Circuits; Digital signal processing; Inverters; Leakage current; Low voltage; Operational amplifiers; Random access memory; Threshold voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.553178

Filename

553178