DocumentCode
1280169
Title
Charge injection error reduction circuit for switched-current systems
Author
Riffaud, P. ; Tourneur, G. ; Garnier, E. ; Roux, P.
Author_Institution
Lab. d´´Etudes de l´´Integration des Composants et Syst., Bordeaux I Univ., Talence, France
Volume
33
Issue
20
fYear
1997
fDate
9/25/1997 12:00:00 AM
Firstpage
1689
Lastpage
1691
Abstract
The authors propose a novel circuit for reducing the charge injection error based on the technique of current source replication, applied to a second generation memory cell. Using the proposed circuit, offset error, linear gain error, and total harmonic distortion are significantly reduced to the detriment of the occupied die area and the power dissipation which are multiplied by a factor of three
Keywords
CMOS analogue integrated circuits; electric charge; errors; harmonic distortion; switched current circuits; CMOS SI circuits; THD reduction; charge injection error reduction circuit; current source replication; die area; linear gain error; offset error; power dissipation; second generation memory cell; switched-current systems; total harmonic distortion;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19971172
Filename
629533
Link To Document