Analysis and prevention of DRAM latch-up during power-on

The occasional power-on latch-up phenomenon of DRAM modules with a data bus shared by multiple DRAM chips on different modules was investigated and the circuit techniques for latch-up prevention were presented. Through HSPICE simulations and measurements, the latch-up triggering source was identified-to be the excessive voltage drop at the n-well pick-up of the CMOS transmission gate of read data latch circuit due to the short-circuit current which flows when the bus contention occurs during power-on. By extracting the HSPICE Gummel-Poon model parameters of the parasitic bipolar transistors of DRAM chips from the measured I-V and C-V data, HSPICE simulations were performed for the power-on latch-up phenomenon of DRAM chips. Good agreements were achieved between measured and simulated voltage waveforms. In order to prevent the power-on latch-up even when the control signals (RAS, GAS) do not track with the power supply, two circuit techniques were presented to solve the problem. One is to replace the CMOS transmission gate by a CMOS tristate inverter in the DRAM chip design and the other is to start the CAS-BEPORE-RAS (CBR) refresh cycle during power-on and thus disable all the Dout buffers of DRAM chips during the initial power-on period