A new self-consistent modeling approach to investigating MOSFET degradation

Author

Hänsch, W. ; Schwerin, A.V. ; Hofmann, F.

Author_Institution

Siemens AG, Munchen, West Germany

Volume

11

Issue

9

fYear

1990

Firstpage

362

Lastpage

364

Abstract

A modeling tool is presented that allows a complete analysis of a DC stress experiment without assuming the location and amount of trapped oxide charges and interface states. To describe the buildup of oxide damage, a semiempirical rate equation approach is outlined. A completely self-consistent calculation is presented of the time dependence of the DC stress experiment. This calculation monitors the amount and location of charges built up in the 2-D oxide region during the stress line. The model includes competing trap mechanisms such as the formation of interface states and fixed oxide traps. This permits consideration of n- and p-channel MOSFETs with the same model. The calculations are compared to DC stress measurements on n- and p-channel devices with gate lengths of 0.65 mu m that are typical for 16-Mb DRAMs.<>

Keywords

DRAM chips; MOS integrated circuits; VLSI; insulated gate field effect transistors; integrated memory circuits; semiconductor device models; 0.65 micron; 16 Mbit; 16-Mb DRAMs; 2-D oxide region; DC stress experiment; DC stress measurements; MOSFET degradation; buildup of oxide damage; competing trap mechanisms; complete analysis; completely self-consistent calculation; fixed oxide traps; formation of interface states; location of charges; modeling tool; n-channel MOSFETs; p-channel MOSFETs; self-consistent modeling approach; semiempirical rate equation; stress line; submicron gate lengths; time dependence; trapped oxide charges; Degradation; Electron traps; Equations; Guidelines; Interface states; MOSFET circuits; Random access memory; State feedback; Stress measurement; Substrates;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.62956

Filename

62956