Title :
The COB stack DRAM cell at technology node below 100 nm-scaling issues and directions
Author :
Kim, Kinam ; Jeong, Moon-Young
Author_Institution :
Technol. Dev., Samsung Electron. Co. Ltd., Kyungki, South Korea
fDate :
5/1/2002 12:00:00 AM
Abstract :
The scaling of the 8F2 COB stack DRAM cell down to 70-nm technology node is described. Issues and possible solutions regarding critical points, such as the difficulty in achieving sufficient memory cell capacitance, degraded cell transistor performance, and increased junction leakage current at storage node are investigated. Although its unit cell size is bigger than those of open bit line cell architectures, the 8F2 COB stack cell can be the most suitable technology for 70-mn DRAM technology node due to its excellent noise immunity and large capacitor area
Keywords :
DRAM chips; MIM devices; capacitance; integrated circuit noise; isolation technology; leakage currents; 70 nm; 70-nm technology node; MIM high-K dielectric capacitor; MSE-STI isolation; capacitor area; capacitor over bitline stack DRAM cell; critical points; degraded cell transistor performance; hierarchical bit line technology; inner-cylinder-type storage node; junction leakage current; memory cell capacitance; noise immunity; planar memory transistor; scaling down; spike-doped channel; storage node junction; substrate doping density; unit cell size; Capacitance; Degradation; Dielectrics; Leakage current; Lithography; MIM capacitors; Paper technology; Random access memory; Semiconductor device noise; Transistors;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
