A novel power-off mode for a battery-backup DRAM

This paper proposes a new DRAM power-off mode, in which the power source is completely shut off during the standby cycle, resulting in a zero standby leakage current. By introducing a new word-line power-off/on sequence and a grounded cell plate technique, all cell data are maintained after power source is turned off and on. Although the proposed mode requires a power-on current, an average standby leakage current is reduced by a factor of 1000, and the total standby current including both the leakage current and refresh current is reduced by a factor of 10 in a 1 Gb DRAM. The proposed circuit technique was verified by a 64 Kb DRAM test chip. All cell data were successfully maintained after the power source switching. The measured power-off time was as long as the measured data retention time in the conventional DRAM standby mode