A novel power-off mode for a battery-backup DRAM

Author

Takashima, Daisaburo ; Oowaki, Yukihito

Author_Institution

ULSI Res. Labs., Toshiba Corp., Kawasaki, Japan

Volume

32

Issue

1

fYear

1997

fDate

1/1/1997 12:00:00 AM

Firstpage

86

Lastpage

91

Abstract

This paper proposes a new DRAM power-off mode, in which the power source is completely shut off during the standby cycle, resulting in a zero standby leakage current. By introducing a new word-line power-off/on sequence and a grounded cell plate technique, all cell data are maintained after power source is turned off and on. Although the proposed mode requires a power-on current, an average standby leakage current is reduced by a factor of 1000, and the total standby current including both the leakage current and refresh current is reduced by a factor of 10 in a 1 Gb DRAM. The proposed circuit technique was verified by a 64 Kb DRAM test chip. All cell data were successfully maintained after the power source switching. The measured power-off time was as long as the measured data retention time in the conventional DRAM standby mode

Keywords

CMOS memory circuits; DRAM chips; integrated circuit design; integrated circuit reliability; leakage currents; 64 Kbit; average standby leakage current; battery-backup DRAM; data retention time; grounded cell plate technique; power source switching; power-off mode; refresh current; standby cycle; total standby current; zero standby leakage current; Capacitance; Circuit testing; Electronic equipment; Leakage current; Random access memory; Semiconductor device measurement; Subthreshold current; Threshold voltage; Time measurement; Variable structure systems;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.553185

Filename

553185