DocumentCode
1280611
Title
Characterization and modeling of oxide chemical-mechanical polishing using planarization length and pattern density concepts
Author
Ouma, D. Okumu ; Boning, Duane S. ; Chung, James E. ; Easter, William G. ; Saxena, Vivek ; Misra, Sudhanshu ; Crevasse, Annette
Author_Institution
Agere Syst. Inc., Allentown, PA, USA
Volume
15
Issue
2
fYear
2002
fDate
5/1/2002 12:00:00 AM
Firstpage
232
Lastpage
244
Abstract
Chemical-mechanical polishing (CMP) has emerged as the dominant dielectric planarization method due to its ability to reduce topography over longer lateral distances than earlier techniques. However, CMP still suffers from pattern dependencies that result in large variation in polished oxide thickness across typical chips, which can impact circuit performance and yield. A comprehensive semiphysical pattern dependent model of the CMP process, integrated with a parameter extraction and process characterization methodology, has been developed to enable accurate and efficient prediction of post-CMP oxide thickness across patterned chips. In the characterization phase, test wafers are polished to obtain model parameters for the desired CMP process. Standard test layouts have been defined which consist of regions with different feature density and pitch; a new contribution is the inclusion of "step density" structures which provide large abrupt post-CMP thickness variations to improve parameter extraction. The key extracted parameter which characterizes the particular CMP process is the planarization length
Keywords
chemical mechanical polishing; integrated circuit measurement; integrated circuit modelling; integrated circuit testing; integrated circuit yield; semiconductor process modelling; circuit yield; dielectric planarization method; feature density; lateral distances; model parameters; oxide chemical-mechanical polishing; parameter extraction; pattern density; planarization length; polished oxide thickness; process characterization methodology; semiphysical pattern dependent model; step density; test wafers; Chemicals; Circuit optimization; Circuit testing; Dielectrics; Integrated circuit yield; Parameter extraction; Planarization; Predictive models; Semiconductor device modeling; Surfaces;
fLanguage
English
Journal_Title
Semiconductor Manufacturing, IEEE Transactions on
Publisher
ieee
ISSN
0894-6507
Type
jour
DOI
10.1109/66.999598
Filename
999598
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