Title :
Modeling of dry development in bilayer-resist process for 140-nm contact hole patterning
Author :
Hwang, Sung Bo ; Kim, Won D. ; Edgar, Thomas F.
Author_Institution :
Dept. of Chem. Eng., Texas Univ., Austin, TX, USA
fDate :
5/1/2002 12:00:00 AM
Abstract :
The dry development process using SO2-containing plasma for 140-nm hole patterning in a bilayer-resist system was described by a neural network technique in conjunction with a statistical modeling method. The SO2 addition into O2 plasma gave the enhanced anisotropy of 140-nm holes. However, defect (polymeric residue) generation at wide-open areas has been observed as a side effect, driving the need for an accurate model to optimize the process. Empirical nonlinear modeling using neural networks was conducted on the basis of data obtained from statistically designed experiments to investigate the effects of relevant parameters (chamber pressure, plasma-source (TCP) power, bias (bottom power), and O2-SO2 flow rate ratio) on defect (polymeric residue) generation and the anisotropy. The authors have found that the reduction of chamber pressure to 10 mT allows independent control of anisotropy and the defect generation. In addition, neural network modeling in a Bayesian framework gives superior accuracy (R2: ⩾0.9) over statistical modeling using limited experimental data and requires fewer training data to accurately describe the process
Keywords :
Bayes methods; design of experiments; neural nets; photoresists; semiconductor process modelling; 10 mtorr; 140 nm; Bayesian framework; O2-SO2; SO2; anisotropy; bias; bilayer-resist process; chamber pressure; contact hole patterning; defect generation; design of experiment; dry development; flow rate ratio; neural network technique; nonlinear modeling; plasma-source power; polymeric residue; statistical modeling method; wide-open areas; Anisotropic magnetoresistance; Dry etching; Intelligent networks; Neural networks; Optical imaging; Passivation; Plasma applications; Plasma chemistry; Polymers; Resists;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on