Title :
SRAM cell design with minimum number of transistor
Author_Institution :
ECE Dept., Lovely Prof. Univ., Phagwara, India
Abstract :
This paper present Static Random Access Memory (SRAM) cell with minimum number of transistor. A conventional SRAM cell requires 6 transistors having two nodes contains normal and complimented data. The scaling of CMOS technology has significant impacts on working of SRAM cell. In 4T cell reading and writing has been performed by each node separately [1]. In this paper SRAM cell (2T) designed and comparison between them made in terms of power consumed, access time and PDP. A 2T cell contains single node, read and write performed through same node. It is found that in 2T cell area reduces by more than 66% maintaining same access time but at the cost of power consumption.
Keywords :
CMOS digital integrated circuits; SRAM chips; integrated circuit design; 2T cell; 4T cell reading; 4T cell writing; CMOS technology; PDP; SRAM cell design; access time; power consumption; static random access memory cell; Computer architecture; Microprocessors; Power demand; SRAM cells; Transistors; Writing; 6T SRAM Cell; Cadence Virtuoso; SRAM;
Conference_Titel :
Engineering and Computational Sciences (RAECS), 2014 Recent Advances in
Conference_Location :
Chandigarh
Print_ISBN :
978-1-4799-2290-1
DOI :
10.1109/RAECS.2014.6799510
