Title :
A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design
Author :
Jou, Shyh-Jye ; Chen, Chang-Yu ; Yang, En-Chung ; Su, Chau-Chin
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
fDate :
1/1/1997 12:00:00 AM
Abstract :
This paper proposes a new pipelined full-adder circuit structure for the implementation of pipelined arithmetic modules. With both static and dynamic structures, it has the advantages of high operational speed, smallest transistor count, and the low power/speed ratio. The adder cell is then used to design a pipelined 8×8-b multiplier-accumulator (MAC). In this MAC, a special pipelined structure is designed to reduce the latency. The MAC is fabricated in a 0.8-μm single-poly-double-metal CMOS process. The post-layout simulation shows that the pipelined 1-b full adder can work up to 350 MHz with a 3 V power supply. The whole MAC chip that contains 4200 transistors is measured to operate a 125 MHz using 3.3 V power supply
Keywords :
CMOS logic circuits; adders; logic design; multiplying circuits; pipeline arithmetic; 0.8 micron; 125 MHz; 3 V; 3.3 V; 350 MHz; dynamic structure; full adder design; high-speed operation; low-power consumption; pipelined arithmetic modules; pipelined multiplier-accumulator; single-poly-double-metal CMOS process; static structure; Adders; Arithmetic; CMOS process; Circuit simulation; Circuits; Delay; Digital signal processing chips; Logic; MOS devices; Pipelines; Power measurement; Power supplies; Semiconductor device measurement; Switches;
Journal_Title :
Solid-State Circuits, IEEE Journal of
