Q factor damping of anti-resonance peak by variable on-die capacitance

Author

Ichimura, Wataru ; Kiyoshige, Sho ; Terasaki, Masahiro ; Otsuka, Hiroyuki ; Sudo, Toshio

Author_Institution

Shibaura Inst. of Technol., Tokyo, Japan

fYear

2014

fDate

1-4 Sept. 2014

Firstpage

1049

Lastpage

1053

Abstract

Power supply noise has been becoming critical in advanced CMOS digital systems, because power supply noise induces false logic operation and instability. Especially, anti-resonance peaks in power distribution network (PDN) due to the chip-package interaction induce the unwanted power supply fluctuation. In this paper, power supply noises and total impedances of power distribution network (PDN) for the variable structure of on-die capacitances have been examined. In addition, Q factors of anti-resonance peaks for various PDN impedances have been examined by changing the value of on-die capacitance. As a result, it has been proved that Q factors of anti-resonance peaks can be suppressed by increasing on-die capacitance. Furthermore, power supply noise distribution on a chip has been simulated for the various location of noise generating circuits and on-die capacitance.

Keywords

Q-factor; capacitance; circuit noise; integrated circuit interconnections; power supply circuits; PDN impedances; Q factors; advanced CMOS digital systems; anti-resonance peaks; chip-package interaction; noise generating circuits; on-die capacitances; power distribution network; power supply noise distribution; total impedances; unwanted power supply fluctuation; variable structure; Analytical models; Capacitance; Electromagnetic compatibility; Impedance; Integrated circuit modeling; Noise; Power supplies; Anti-resonance peaks; Co-design; Power integrity; Power supply noises; Q factor;

fLanguage

English

Publisher

ieee

Conference_Titel

Electromagnetic Compatibility (EMC Europe), 2014 International Symposium on

Conference_Location

Gothenburg

Type

conf

DOI

10.1109/EMCEurope.2014.6931057

Filename

6931057