DocumentCode
1280931
Title
Power minimisation of VLSI wave digital filters through systolic block size selection
Author
Israsena, P. ; Summerfield, S.
Author_Institution
Sch. of Eng., Warwick Univ., Coventry, UK
Volume
35
Issue
21
fYear
1999
fDate
10/14/1999 12:00:00 AM
Firstpage
1795
Lastpage
1796
Abstract
An investigation into systolic architectures for wave digital filters for low-power applications is presented. Based on a three-port adaptor implementation of the second-order section, minimum power is found using pipelining with a 2 bit block size for which the power consumption is reduced by 50% and the power-area-delay performance increased by 5 times relative to the starting, non-pipelined, implementation
Keywords
VLSI; circuit optimisation; digital integrated circuits; low-power electronics; minimisation; pipeline processing; systolic arrays; wave digital filters; VLSI wave digital filters; low-power applications; pipelining; power consumption reduction; power minimisation; power-area-delay performance; second-order section; systolic block size selection; three-port adaptor implementation;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19991256
Filename
809973
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