A New Method for Layout-Dependent Parasitic Capacitance Analysis and Effective Mobility Extraction in Nanoscale Multifinger MOSFETs

The impact of layout-dependent parasitic capacitances on extraction of inversion carrier density Q_inv and effective mobility μ_eff has been investigated on multifinger MOSFETs. An improved open deembedding method can eliminate the extrinsic parasitic capacitance, and 3-D interconnect simulation is necessary for extraction of intrinsic parasitic capacitances such as gate finger sidewall and finger-end fringing capacitances, i.e., C_of and Cf(poly-end), respectively. Both categories of parasitic capacitance lead to overestimated Q_inv and underestimated μ_eff. The increase in effective channel width W_eff due to ΔW from shallow trench isolation (STI) top-corner rounding may compensate μ_eff degradation due to STI stress. The tradeoff between μ_eff and W_eff determines the impact of width scaling on I_DS and Gm . A new method based on the measured S-parameters, open-M1 deembedding, and Raphael simulation can precisely determine the mentioned parameters associated with the intrinsic channel and realize accurate extraction of μ_eff in multifinger MOSFETs with various layouts and narrow widths down to 0.125 μm.