Title :
Jitter-suppressed low-power 2.5 Gbit/s clock and data recovery IC without high-Q components
Author :
Kishine, Keiji ; Ishihara, Noboru ; Ichino, H.
Author_Institution :
NTT Optical Network Syst. Labs., Kanagawa
fDate :
8/28/1997 12:00:00 AM
Abstract :
A 2.5 bit/s monolithic clock and data recovery (CDR) IC using a PLL technique is fabricated using Si bipolar technology. The CDR IC provides suppressed jitter characteristics with a low power consumption. To our knowledge, this is the first report of a single-chip 2.5 Gbit/s CDR IC, the jitter characteristics of which meet all three types of STM-16 jitter specifications described in ITU-T recommendations
Keywords :
bipolar integrated circuits; digital communication; elemental semiconductors; jitter; mixed analogue-digital integrated circuits; optical receivers; phase locked loops; silicon; timing circuits; 0.4 W; 0.5 micron; 2.5 Gbit/s; ITU-T recommendations; PLL technique; STM-16 jitter specifications; Si; Si bipolar technology; clock recovery IC; data recovery IC; jitter suppression; low-power IC; monolithic IC;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19971052
