Electrostatics of JFET at 6 nm channel length: a simulation study

A junction field effect transistor (JFET) is studies as an alternative device for performing complementary logic currently limited to MOS. Complementary logic with cJFET bult using 60 nm lithography was reported recently. This summarises the simulation results of scaled n-channel JFET with a gate length of 6 nm. The JFET was operated in double gate mode. Results of this simulation study reveal that it is possible to scale JFET gate length to 6 nm operating at 0.5 V and achieve an ion/loff ratio greater than 5000. Threshold voltage can be varied by varying the channel profile. In Essence, JFET needs to be considered as a viable candidate for future scaling.