Low power digital PLL based TDC using low rate clocks

Author

Park, M.J. ; Lee, Jonathan Y. ; Boo, H.H. ; Mhin, B.H. ; Kim, Seong Dae ; Park, M.Y. ; Lee, Chris S. ; Yu, H.K.

Author_Institution

Dept. of Radio Wave Eng., Hanbat Nat. Univ., Daejeon, South Korea

Volume

47

Issue

14

fYear

2011

Firstpage

793

Lastpage

794

Abstract

A time-to-digital converter (TDC) using a low rate clock is presented. A simple TDC, capable of decreasing power consumption and solving the metastability problem by using low-rate clocks to detect the fine fractional time difference between the reference clock and digitally controlled oscillator (DCO) clock, is presented. The proposed TDC also includes a simple DCO clock period (T_v) calculation algorithm. An all-digital phase-locked loop (ADPLL), fabricated in 90 nm CMOS process, dissipates 0.8 mA at 1.2 V, and achieves 6.25 ps period RMS jitter from 2 GHz.

Keywords

CMOS digital integrated circuits; clocks; data conversion; digital phase locked loops; jitter; low-power electronics; CMOS process; RMS jitter; all-digital phase-locked loop; clock period calculation algorithm; current 0.8 mA; digitally controlled oscillator clock; fractional time difference; frequency 2 GHz; low rate clocks; low-power digital PLL; low-rate clocks; reference clock; size 90 nm; time-digital converter; voltage 1.2 V;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el.2011.1426

Filename

5961265