Evaluating programmable logic devices

The use of the combinational/register coordinate system as a graphical way of measuring programmable logic devices (PLDs) in terms of gates and registers is reviewed. It is assumed that the I/O resources of the PLD, which constitute a third axis, are adequate. This allows the analysis to be restricted to an x-y plane fixed along the z-axis. The device´s application area, which is the area bounded by its combinational and register capability, is discussed, and methods for calculating the application range are described. Three brief examples demonstrate the ways in which the coordinate system might be used in CAD tools that automate the PLD design process.<>