DocumentCode :
1282873
Title :
Wire-sizing optimization with inductance consideration using transmission-line model
Author :
Gao, Youxin ; Wong, D.F.
Author_Institution :
Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
Volume :
18
Issue :
12
fYear :
1999
fDate :
12/1/1999 12:00:00 AM
Firstpage :
1759
Lastpage :
1767
Abstract :
Because of the inaccuracy of the Elmore delay model and its inability to handle inductance, it is necessary to use a more accurate delay model in wire-sizing optimization. This paper presents continuous wire-sizing optimization by using a three pole based delay model. Our work is focused on exponential wire shape f(x)=ae-bx, i.e, we determine a and b such that either delay or area is minimized. Fringing capacitance and inductance, which have been neglected in previous work on wire sizing, are taken into consideration in the delay model. Expressions involved in calculating all three poles are derived with the help of the Picard-Carson method. Since these expressions are all analytical, the delay calculation is very efficient. In our experiments, the delay model is found to be far more accurate than the Elmore delay model. We also observe that in determining the optimal shape that minimizes delay, the Elmore delay model performs as well as our delay model. However, in determining the optimal shape that minimizes area subject to a delay bound, the Elmore delay model performs much worse than our delay model
Keywords :
VLSI; capacitance; circuit layout CAD; circuit optimisation; delay estimation; inductance; integrated circuit layout; transmission line theory; Picard-Carson method; VLSI layout; area minimisation; delay bound; delay calculation; fringing capacitance; inductance; optimal shape; three pole based delay model; transmission-line model; wire-sizing optimization; Capacitance; Delay effects; Delay estimation; Inductance; Integrated circuit interconnections; Shape; Transient response; Transmission lines; Very large scale integration; Wire;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.811325
Filename :
811325
Link To Document :
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