Title :
A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation
Author :
Zhu, Yan ; Chan, Chi-Hang ; Sin, Sai-Weng ; U, Seng-Pan ; Martins, Rui Paulo ; Maloberti, Franco
Author_Institution :
State-Key Lab. of Analog & Mixed Signal VLSI, Univ. of Macau, Macao, China
Abstract :
This paper presents a time-interleaved pipelined-SAR ADC with on-chip offset cancellation technique. The design reuses the SAR ADC to perform offset cancellation, thus saving calibration costs. The inter-stage gain of 8 is implemented in a 6-bit capacitive DAC with a flip-around operation. A capacitive attenuation used in both the first and second DACs significantly reduces the power dissipation and optimizes conversion speed. The detailed circuit implementation of the subthreshold op-amp is discussed, and the possible limits caused by nonidealities are analyzed for a proper correction in the design. These include the inter-stage-gain error and various channel mismatches of offset, gain, and timing. Measurements of a 65-nm CMOS prototype operating at 160 MS/s and 1.1-V supply show an SNDR of 55.4 dB and 2.72 mW total power consumption.
Keywords :
CMOS integrated circuits; analogue-digital conversion; digital-analogue conversion; operational amplifiers; CMOS prototype; SNDR; calibration costs; capacitive DAC; capacitive attenuation; interstage-gain error; on-chip offset cancellation technique; pipelined-SAR ADC decoupled flip-around MDAC; power 2.72 mW; power dissipation; self-embedded offset cancellation; size 65 nm; subthreshold op-amp; successive approximate register; time-interleaved pipelined-SAR ADC; voltage 1.1 V; word length 10 bit; word length 6 bit; Accuracy; Arrays; Calibration; Capacitance; Capacitors; Gain; Timing; ${rm V}_{rm DD}$ -attenuator; Decoupled flip-around MDAC; offset-cancellation; pipelined-SAR ADC;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2012.2211695
