3-D Vertical FG nand Flash Memory With a Novel Electrical S/D Technique Using the Extended Sidewall Control Gate

We propose a novel 3-D vertical floating-gate (FG) nand Flash memory cell array with a novel electrical source/drain (S/D) technique using extended sidewall control gates (ESCGs). A cylindrical FG structure is implemented to overcome the reliability issues of charge-trap-type cells. A novel electrical S/D layer by the ESCG structure also allows enhancement-mode operation. With this novel structure, we successfully demonstrate normal Flash cell operation with high-speed programming and superior read currents due to both the increase in coupling ratio and the use of low resistive electrical S/D technique by device simulation. Moreover, we found that the 3-D vertical Flash memory cell array with the novel electrical S/D technique had less interference with neighboring cells by about 50% in comparison with the conventional 3-D vertical FG nand cell array without an ESCG. Above all, the proposed cell array is one of the candidates for a Terabit 3-D vertical nand Flash cell array with high-speed read/program operation and high reliability.