A poly-framed LDD sub-half-micrometer CMOS technology

Author

Pfiester, James R. ; Crain, Eil ; Lin, Jung-Hui ; Gunderson, Craig D. ; Kaushik, Vidya

Author_Institution

Motorola Inc., Austin, TX, USA

Volume

11

Issue

11

fYear

1990

Firstpage

529

Lastpage

531

Abstract

A novel LDD spacer technology that uses disposable silicon nitride spacers on a sacrificial polysilicon frame has been developed for a sub-half-micrometer CMOS technology. An improvement in short-channel behavior is achieved due to a reduction in lateral LDD n/sup -/ and p/sup -/ diffusion, and the effect of substrate bias on the drain junction leakage caused by sidewall spacer formation is eliminated. The DC hot-carrier lifetime for the 0.3- mu m-channel-length poly-framed LDD NMOS devices, defined as the time associated with a 10% shift in peak transconductance, is in excess of 10 years for a power supply voltage of 3.3 V.<>

Keywords

CMOS integrated circuits; VLSI; integrated circuit technology; semiconductor technology; 0.3 micron; 10 y; 3.3 V; DC hot-carrier lifetime; LDD spacer technology; device lifetime; disposable Si/sub 3/N/sub 4/ spacers; poly-framed LDD; polycrystalline Si; power supply voltage; sacrificial polysilicon frame; short channel behaviour improvement; sub-half-micrometer CMOS technology; Annealing; Boron; CMOS technology; Diodes; Hot carriers; Implants; MOSFET circuits; Silicon; Space technology;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.63022

Filename

63022