Simplified 0.35-μm flash EEPROM process using high-temperature oxide (HTO) deposited by LPCVD as interpoly dielectrics and peripheral transistors gate oxide

Author

Candelier, P. ; Mondon, F. ; Guillaumot, B. ; Reimbold, G. ; Martin, F.

Author_Institution

CEA LETI, Grenoble, France

Volume

18

Issue

7

fYear

1997

fDate

7/1/1997 12:00:00 AM

Firstpage

306

Lastpage

308

Abstract

A simplified flash EEPROM process was developed using high-temperature LPCVD oxide both as flash cells interpoly dielectrics and as peripheral transistors gate oxide (decoding logic). An O/sub 2/ anneal at 850/spl deg/C lowers charge trapping and interface trap density induced by Fowler-Nordheim injection. However, electron trapping remains slightly higher than with dry thermal oxide. Similar memory charge loss and write-erase endurance are obtained as for ONO-insulated cells. HTO thus proves to have the required quality and reliability to be used in flash EEPROMs.

Keywords

CMOS memory circuits; EPROM; annealing; chemical vapour deposition; dielectric thin films; electron traps; integrated circuit reliability; interface states; 0.35 mum; 850 C; Fowler-Nordheim injection; LPCVD; O/sub 2/; O/sub 2/ anneal; Si-SiO/sub 2/; charge trapping; decoding logic; electron trapping; flash EEPROM process; high-temperature oxide; interface trap density; interpoly dielectrics; memory charge loss; peripheral transistors gate oxide; reliability; write-erase endurance; Annealing; Capacitors; Current measurement; Density measurement; Dielectrics; EPROM; Electron traps; Interface states; Monitoring; Oxidation;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.596920

Filename

596920