A novel pseudo-floating-gate flash EEPROM device (/spl Psi/-cell)

Author

Papadas, C. ; Guillaumot, B. ; Cialdella, B.

Author_Institution

Central R&D Technol., SGS-Thomson Microelectron., Crolles, France

Volume

18

Issue

7

fYear

1997

fDate

7/1/1997 12:00:00 AM

Firstpage

319

Lastpage

322

Abstract

The purpose of this paper is to present a novel Pseudo-Floating-Gate Flash EEPROM cell which has certain advantages over the classical structure and, therefore, it seems adequate for multi-MBit memory arrays as well as for CMOS embedded memory applications. The proposed cell is based on the series resistance modification concept and exhibits the following characteristics: 1) simplicity, 2) dimensions as small as a MOSFET, 3) the ability to follow the shrink rate of CMOS devices, 4) the ability to be easily embedded in CMOS, 5) low-power compatibility, and 6) insensitivity to depletion phenomena. All these features make this device very attractive for future NVM applications.

Keywords

CMOS memory circuits; EPROM; integrated circuit measurement; /spl Psi/-cell; CMOS device shrink rate; CMOS embedded memory; MOSFET dimensions; depletion phenomena insensitivity; low-power compatibility; multi-MBit memory arrays; nonvolatile memory; pseudo-floating-gate flash EEPROM device; series resistance modification concept; simplicity; transient programming characteristics; CMOS process; CMOS technology; Character generation; EPROM; Electrons; MOSFET circuits; Microelectronics; Nonvolatile memory; Research and development; Size control;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.596924

Filename

596924