Thin-oxide silicon-gate self-aligned 6H-SiC MOSFETs fabricated with a low-temperature source/drain implant activation anneal

We have demonstrated self-aligned (SA) n+ polysilicon gate n-channel inversion MOSFETs in 6H-SiC with 25-nm thick gate oxides. The nitrogen-implanted source/drain regions were activated with a furnace anneal at 1050/spl deg/C. These devices exhibit a positive threshold voltage (about +1 V), and peak transconductance of 3.6 mS/mm at V/sub g/=7 V, comparable to the best nonself-aligned 6H-SiC MOSFETs. The subthreshold slope is 200 mV/decade, about two times higher than that of typical silicon MOSFETs. This represents the first demonstration of a viable process for silicon-gate self-aligned MOSFETs in 6H-SiC.