DocumentCode
128746
Title
Parallel elite genetic algorithm for test scheduling of SoC
Author
Guangyu Liu
Author_Institution
Shenzhen Grad. Sch., Sch. of Electron. & Comput. Eng., Peking Univ., Shenzhen, China
fYear
2014
fDate
9-11 June 2014
Firstpage
1985
Lastpage
1988
Abstract
Test scheduling is an important issue for testing the SoC (system-on-chip). This work uses a parallel elite genetic algorithm for test scheduling to reduce the test application time under the peak power constraint. It is applied to the 2D SoC and experimental results on benchmark circuits show that it is one of the most effective algorithms in solving the problem.
Keywords
genetic algorithms; integrated circuit testing; scheduling; system-on-chip; 2D SoC; benchmark circuits; parallel elite genetic algorithm; peak power constraint; system-on-chip; test scheduling; Genetic algorithms; Processor scheduling; Resource management; Scheduling; Sociology; System-on-chip; Testing; SoC testing; parallel elite genetic algorithm; test scheduling;
fLanguage
English
Publisher
ieee
Conference_Titel
Industrial Electronics and Applications (ICIEA), 2014 IEEE 9th Conference on
Conference_Location
Hangzhou
Print_ISBN
978-1-4799-4316-6
Type
conf
DOI
10.1109/ICIEA.2014.6931494
Filename
6931494
Link To Document