Title :
Low-jitter design method based on Wn-domain jitter analysis for 10 Gbit/s clock and data recovery ICs
Author :
Kishine, Keiji ; Inaba, Hiromi ; Nakamura, Mitsutoshi ; Nakamura, Mitsutoshi ; Ohtomo, Y. ; Onodera, Hidetoshi
Author_Institution :
Univ. of Shiga Prefecture, Hikone, Japan
Abstract :
A low-jitter design method based on omegan-domain jitter analysis for the clock and data recovery (CDR) ICs using the linear phase-locked loop (PLL) is proposed. Using this method, the loop parameters of the PLL can be optimised, which makes it possible to design the CDR IC for various targets.
Keywords :
clock and data recovery circuits; integrated circuit design; jitter; phase locked loops; CDR IC; clock and data recovery IC; linear phase-locked loop; loop parameter; low-jitter design; omegan-domain jitter analysis;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2009.0717
