DocumentCode
1287996
Title
PARE: instruction set architecture for efficient code size reduction
Author
Kwon, Young-Jim ; Ma, Xiarong ; Lee, Hyuk Jae
Author_Institution
MIPS Technol. Inc., Mountain View, CA, USA
Volume
35
Issue
24
fYear
1999
fDate
11/25/1999 12:00:00 AM
Firstpage
2098
Lastpage
2099
Abstract
To achieve efficient code size reduction, a new instruction set architecture and a register allocation technique optimised for the architecture are proposed. Experiments show that the efficiency of the code size reduction is improved by an average of 13.8% when compared with that of the conventional approach
Keywords
computer architecture; embedded systems; instruction sets; PARE; code size reduction; embedded systems; instruction set architecture; partitioned registers extension; reduction efficiency; register allocation technique;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19991420
Filename
815916
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