Title :
PARE: instruction set architecture for efficient code size reduction
Author :
Kwon, Young-Jim ; Ma, Xiarong ; Lee, Hyuk Jae
Author_Institution :
MIPS Technol. Inc., Mountain View, CA, USA
fDate :
11/25/1999 12:00:00 AM
Abstract :
To achieve efficient code size reduction, a new instruction set architecture and a register allocation technique optimised for the architecture are proposed. Experiments show that the efficiency of the code size reduction is improved by an average of 13.8% when compared with that of the conventional approach
Keywords :
computer architecture; embedded systems; instruction sets; PARE; code size reduction; embedded systems; instruction set architecture; partitioned registers extension; reduction efficiency; register allocation technique;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19991420
