Title :
Synchronising logic gates for wave-pipelining design
Author :
Xia, Zhihua ; Ishihara, Sayaka ; Hariyama, Masanori ; Kameyama, Michitaka
Author_Institution :
Grad. Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
Abstract :
Synchronising logic gates (SLGs) used for a wave-pipelining design are presented. An SLG is a dual-rail logic gate which has an almost constant gate delay and can be used as an intermediate latch to synchronise data paths. Based on the SLGs, the wave-pipelining circuits are easily designed without complicated timing analysis. To evaluate the SLGs, an 8 × 8 multiplier is designed using a 90 nm design rule. The multiplier works well at 3.57 GHz.
Keywords :
logic design; logic gates; multiplying circuits; synchronisation; SLG; constant gate delay; dual-rail logic gate; frequency 3.57 GHz; intermediate latch; multiplier; size 90 nm; synchronise data paths; synchronising logic gates; timing analysis; wave-pipelining circuits; wave-pipelining design;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2010.1602
