Title :
Scalable frame-synchronisation circuit for highly parallel optical interconnections [ATM]
Author :
Yamakoshi, K. ; Kawano, R. ; Yamanaka, N.
Author_Institution :
NTT Network Service Syst. Lab., Tokyo, Japan
fDate :
11/25/1999 12:00:00 AM
Abstract :
A scalable frame-synchronisation circuit is proposed for highly parallel high-speed optical interconnections. Its scalable architecture enables the number of channels to be increased without any decrease in the transmission rate. In HSPICE circuit simulations, a circuit using 0.2 μm CMOS technology compensated for a skew in 622 Mbit/s input data
Keywords :
SPICE; asynchronous transfer mode; compensation; optical interconnections; synchronisation; 0.25 micron; 622 Mbit/s; CMOS technology; HSPICE circuit simulations; high-speed optical interconnections; highly parallel optical interconnections; input data; scalable frame-synchronisation circuit; skew compensation; transmission rate;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19991434
