Title :
fT integration employing lateral pnps in BiCMOS/CMOS technologies
Author :
Khumsat, P. ; Worapishet, A. ; Payne, A.J.
Author_Institution :
Dept. of Electr. & Electron. Eng., Imperial Coll. of Sci., Technol. & Med., London, UK
fDate :
11/25/1999 12:00:00 AM
Abstract :
The use of lateral pnp transistors commonly existing in BiCMOS processes to improve fT-integrator performance in terms of the tuning range and power consumption over that of previous npn-only circuits is presented. The complementary employment of npn-pnp devices also leads to an alternative fT integrator architecture that further reduces power and silicon area. Simulated performances indicate a tuning range improvement by a factor of 1.7-2.6 with total harmonic distortion (THD) of <-40 dB up to 50% modulation depth. The feasibility of using only the lateral devices to implement an fT integrator in a pure digital CMOS technology is also discussed
Keywords :
BiCMOS analogue integrated circuits; CMOS analogue integrated circuits; bipolar transistors; circuit tuning; harmonic distortion; integrating circuits; BiCMOS technology; CMOS technology; circuit simulation; fT integrator; frequency tuning range; parasitic lateral pnp transistor; power consumption; silicon area; total harmonic distortion;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19991450
