• DocumentCode
    1288281
  • Title

    Accurate Current Estimation for Interconnect Reliability Analysis

  • Author

    Jain, Palkesh ; Jain, Ankit

  • Author_Institution
    External Design & Manuf. (EDM) Group, Texas Instrum. India, Bangalore, India
  • Volume
    20
  • Issue
    9
  • fYear
    2012
  • Firstpage
    1634
  • Lastpage
    1644
  • Abstract
    An improved and efficient method for static estimation of average and root-mean-squared currents used for electromigration (EM) reliability analysis is presented in this work. Significantly different from state-of-the-art, the proposed method gives closed-form expressions for average and RMS currents in one complete cycle. The proposed method can be readily configured to work with different combinations of ramp and exponential waveforms. Subsequently, the inadequacies of using conventional EM-severity metrics: either the net´s lumped capacitance or the net´s effective capacitance, along with the regular timing slew, for EM analysis are outlined. As a correction, and, application of proposed method, we provide formulations for deriving the effective “EM” slew, which can be used with conventional approaches to accurately compute the currents. Further, unlike traditional wisdom, we note that not just the RMS current, but even the total charge transfer can depend on the waveform type, and propose formulations to that regard. Additionally, for the first time, we present a method for incorporating the driver´s dynamic IR drop while computing RMS currents. Alongside, we lay recommendations for ensuring the standard-cell EM safety at chip level. Finally, we share model-validation results from a production 40 nm design, enabling a 40% higher performance closure.
  • Keywords
    electromigration; integrated circuit interconnections; integrated circuit reliability; mean square error methods; RMS currents; average current static estimation; chip level; closed-form expressions; dynamic IR drop; electromigration reliability analysis; exponential waveforms; interconnect reliability analysis; net effective capacitance; net lumped capacitance; production design; ramp waveforms; root-mean-squared current static estimation; size 40 nm; standard-cell EM safety; total charge transfer; waveform type; Computational modeling; Driver circuits; Estimation; Integrated circuit interconnections; Mathematical model; Reliability; Switches; Aging; degradation; electromigration; interconnects; reliability; variability;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2011.2160882
  • Filename
    5970101