A 2.4 GHz Fractional-N Frequency Synthesizer With High-OSR ΔΣ Modulator and Nested PLL

Author

Park, Pyoungwon ; Park, Dongmin ; Cho, SeongHwan

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., KAIST, Daejeon, South Korea

Volume

47

Issue

10

fYear

2012

Firstpage

2433

Lastpage

2443

Abstract

This paper presents a nested-PLL architecture for a low-noise wide-bandwidth fractional-N frequency synthesizer. In order to reduce the quantization noise, operating frequency of ΔΣ modulator (DSM) is increased by using an intermediate output of feedback divider. A PLL which serves as an anti-alias filter is added to suppress noise aliasing caused by the divider. Prototype implemented in a 0.13 μm CMOS using ring VCOs achieves 26.3 dB of quantization noise suppression while consuming 15.2 mW and occupying 0.17 mm².

Keywords

CMOS integrated circuits; circuit feedback; circuit noise; delta-sigma modulation; filters; frequency synthesizers; modulators; phase locked loops; quantisation (signal); CMOS; DSM; antialias filter; feedback divider; frequency 2.4 GHz; high-OSR ΔΣ modulator; low-noise wide-bandwidth fractional-N frequency synthesizer; nested-PLL architecture; noise aliasing suppression; noise figure 26.3 dB; power 15.2 mW; quantization noise suppression; ring VCO; size 0.13 mum; Bandwidth; Charge pumps; Phase locked loops; Phase noise; Quantization; Stability analysis; Fractional-N frequency synthesizer; high-OSR DSM; nested-PLL; quantization noise reduction;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2012.2209809

Filename

6308731