A high yield buried p-layer fabrication process for GaAs LSI circuits

GaAs MESFETs for LSI and VLSI require high transconductance to drive large wiring loads, but they must also exhibit extremely good uniformity and reproducibility. To provide ion-implanted MESFETs that meet these conflicting needs, the authors developed a 0.7-μm buried p-layer (BP) multifunction self-aligned gate (MSAG) fabrication process which has demonstrated excellent yields for circuits of up to 5000 gates. Device and circuit performance has been studied as a function of BP implant dose. LSI circuit yield and performance have been characterized using 4×4-, 8×8-, 12×12-, 16×16-, and 20×20-bit parallel-array multipliers on the same die. A high-dose BP implant has resulted in σV_T as low as 8 mV over 3-in wafers and 20×20-bit multipliers with self-test yields of 61%. Measured worst-case multiplication times range from 870 ps for the 4×4-bit to 6.5 ns for the 20×20-bit multipliers, representing record speeds for these multipliers. The average gate delays for these multipliers are 51 to 67 ps, the fastest extracted gate delays reported for LSI circuits