A 2.5-Gb/s On-Chip Interconnect Transceiver With Crosstalk and ISI Equalizer in 130 nm CMOS

Author

Lee, Jaewon ; Lee, Woojae ; Cho, SeongHwan

Author_Institution

Dept. of Electr. Eng., KAIST, Daejeon, South Korea

Volume

59

Issue

1

fYear

2012

Firstpage

124

Lastpage

136

Abstract

In this paper, a crosstalk compensation scheme for high speed single-ended on-chip signaling is presented. To reduce the effect of crosstalk in bandwidth enhanced channel employing capacitively driven interconnect, a crosstalk feed-forward equalizer is proposed, which compensates for the low-pass nature of the crosstalk. The proposed scheme is verified using a three-channel 10 mm on-chip interconnect implemented in 130 nm CMOS process. Measurement results show that the proposed transceiver effectively removes the crosstalk for data rates of up to 2.5-Gb/s while consuming 0.96 mW, which corresponds to energy efficiency of 0.41 pJ/bit.

Keywords

CMOS integrated circuits; compensation; crosstalk; equalisers; feedforward; integrated circuit interconnections; intersymbol interference; radio transceivers; radiofrequency integrated circuits; CMOS process; ISI equalizer; bit rate 2.5 Gbit/s; capacitive driven interconnect; crosstalk compensation scheme; crosstalk feed-forward equalizer; high speed single-ended on-chip signaling; on-chip interconnect transceiver; power 0.96 mW; size 10 mm; size 130 nm; three-channel on-chip interconnect; Capacitance; Crosstalk; Equalizers; Integrated circuit interconnections; Metals; System-on-a-chip; Transfer functions; Capacitively driven interconnect; ISI compensation; Network-On-Chip (NOC); crosstalk compensation; equalizer; global signaling; on-chip interconnect;

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2011.2161394

Filename

5971790