• DocumentCode
    1289501
  • Title

    Two-dimensional analysis and design considerations of high-voltage planar junctions equipped with field plate and guard ring

  • Author

    Goud, C. Basavana ; Bhat, K.N.

  • Author_Institution
    Dept. of Electr. Eng., Indian Inst. of Technol., Madras, India
  • Volume
    38
  • Issue
    6
  • fYear
    1991
  • fDate
    6/1/1991 12:00:00 AM
  • Firstpage
    1497
  • Lastpage
    1504
  • Abstract
    The breakdown voltages of planar junctions (both nonpunchthrough and punchthrough cases) equipped with field plates and guard rings are determined by evaluating the ionization integral using the potential distribution computed by solving Poisson´s equation in two-dimensions by a finite difference method. The influence of various parameters, such as substrate doping concentration, n-layer thickness, field oxide thickness, cylindrical junction curvature, field plate width, and the spacing between field plate and guard ring, on the breakdown voltage is extensively studied. It is shown that an optimum value exists for the field oxide thickness to realize maximum breakdown voltage. The study also shows that the optimum oxide thickness depends upon cylindrical junction curvature, substrate doping concentration, and n-layer thickness. It is further shown that the permittivity of a passivant dielectric layer deposited over field plate structure influences the breakdown voltage when breakdown takes place at the field plate edge. The numerical results are compared with the experimental data, and good agreement between the two is observed. Based on this two-dimensional study, design guidelines are provided for achieving breakdown voltages close to maximum realizable values, by conserving the device area and reducing the ionization at the field plant edge. The results presented clearly demonstrate the superiority of the field plate design using punchthrough structures over nonpunchthrough structures in realizing a given breakdown voltage
  • Keywords
    insulated gate field effect transistors; power transistors; semiconductor device models; 2D model; Poisson´s equation; breakdown voltages; cylindrical junction curvature; design guidelines; device area; experimental data; field oxide thickness; field plate; field plate width; finite difference method; guard ring; high-voltage planar junctions; ionization integral; n-layer thickness; numerical results; passivant dielectric layer; permittivity; power MOSFET; punchthrough structures; spacing; substrate doping concentration; Breakdown voltage; Dielectric breakdown; Dielectric substrates; Distributed computing; Doping; Finite difference methods; Integral equations; Ionization; Permittivity; Poisson equations;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/16.81645
  • Filename
    81645