Title :
Clock/data recovery PLL using half-frequency clock
Author :
Rau, M. ; Oberst, T. ; Lares, R. ; Rothermel, A. ; Schweer, R. ; Menoux, N.
Author_Institution :
Ulm Univ., Germany
fDate :
7/1/1997 12:00:00 AM
Abstract :
A CMOS clock and data recovery PLL is described for serial nonreturn-to-zero (NRZ) data transmission. The voltage controlled oscillator (VCO) works at half the data rate, which means for a 1-Gb/s data rate, the VCO runs at 500 MHz. A specially designed phase comparator uses a delay-locked loop (DLL) to generate the required sampling clocks to compare clock and data. The VCO can typically be tuned from 350 MHz to 890 MHz, and the phase-locked loop (PLL) locks between 720 Mb/s and 1.3 Gb/s. Data recovery is error free up to 1.2 Gb/s with a 9-b pseudorandom data sequence. The core consumes 85 mW (3.3 V) at 1 Gb/s
Keywords :
CMOS digital integrated circuits; clocks; delay circuits; digital phase locked loops; phase comparators; voltage-controlled oscillators; 3.3 V; 350 to 890 MHz; 720 Mbit/s to 1.3 Gbit/s; 85 mW; clock/data recovery PLL; data rate; delay-locked loop; error-free data recovery; half-frequency clock; phase comparator; pseudorandom data sequence; sampling clocks; serial nonreturn-to-zero data transmission; voltage controlled oscillator; Circuits; Clocks; Data communication; Delay; Detectors; Optical signal processing; Phase detection; Phase locked loops; Sampling methods; Voltage-controlled oscillators;
Journal_Title :
Solid-State Circuits, IEEE Journal of
