DocumentCode :
128991
Title :
DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energy
Author :
Jaksic, Zoran ; Canal, Ramon
Author_Institution :
Dept. of Comput. Archit., Univ. Politec. de Catalunya, Barcelona, Spain
fYear :
2014
fDate :
24-28 March 2014
Firstpage :
1
Lastpage :
4
Abstract :
Recent technology trends has turned DRAMs into an interesting candidate to substitute traditional SRAM-based on-chip memory structures (i.e. register file, cache memories). Nevertheless, a major problem to introduce these cells is that they lose their state (i.e. value) over time, and they have to be refreshed. This paper proposes the implementation of coherent caches with DRAM cells. Furthermore, we propose to use the coherence state to tune the refresh overhead. According to our analysis, an average of up to 57% of refresh energy can be saved. Also, comparing to the caches implemented in SRAMs total energy savings are on average up to 39% depending of the refresh policy with a performance loss below 8%.
Keywords :
DRAM chips; SRAM chips; cache storage; protocols; DRAM-based coherent caches; SRAM-based on-chip memory structures; coherence protocol; energy savings; Benchmark testing; Coherence; FinFETs; Protocols; Random access memory; System performance; 3T DRAM; 6T SRAM; FinFETs; cache coherence; retention time;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014
Conference_Location :
Dresden
Type :
conf
DOI :
10.7873/DATE.2014.094
Filename :
6800295
Link To Document :
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