Title :
PIER: an early treatment of inter-process interactions
Author :
Beck, Ted J. ; Losleben, Paul ; Saraswat, Krishna C.
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., CA, USA
fDate :
2/1/1997 12:00:00 AM
Abstract :
The period of maximum profitability in semiconductor products is short and occurs early in production, thereby forcing the industry to continually strive to reduce the development time for new process flows. Described in this paper is the Process Integration Engineers´ Resource (PIER), currently being developed at Stanford University, which is intended to assist the process integration engineer in the specification of process targets and the timely completion of process integration. The approach taken by this software tool is based on an early analysis of inter-process interactions and aids in the scheduling of process module development. The tool is employed prior to complete target specification, and a qualitative simulation of the skeletal process flow is used to identify all modeled inter-process interactions for an arbitrary flow. Predefined interaction models and the simulated wafer conditions enable this interaction identification. A semantic network representing the critical dependencies between processes resulting from the Identified interactions is then constructed. An understanding of the interactions and process dependencies is expected to improve the development of the flow in four ways: (1) potential flow design errors are more easily identified before process target specification; (2) more complete information is provided to the unit process engineers; (3) ramifications of subsequent process changes are identified; and (4) a partially ordered graph of processes allows for improved process sequences for the flow´s target specification and development
Keywords :
semiconductor process modelling; PIER; development time; inter-process interactions; process flow; process integration; process module; scheduling; semantic network; semiconductor product; software tool; wafer simulation; Design engineering; Electronics industry; Fabrication; Job shop scheduling; Logic; Production; Profitability; Random access memory; Semiconductor device modeling; Software tools;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on