Silicon Nanowire Tunnel FETs: Low-Temperature Operation and Influence of High- $k$ Gate Dielectric

In this paper, we demonstrate p-channel tunnel FETs based on silicon nanowires grown with an in situ p-i-n doping profile. The tunnel FETs were fabricated with three different gate dielectrics, SiO₂, Al₂O₃, and HfO₂, and show a performance enhancement when using high-k dielectric materials. The best performance is achieved for the devices using HfO₂ as the gate dielectric, which reach an I_on of 0.1 μA/μm (V_DS = -0.5 V, V_GS = -2 V), combined with an average inverse subthreshold slope (SS) of ~ 120 mV/dec and an I_on/I_off ratio of around 10⁶. For the tunnel FETs with Al₂O₃ as the gate dielectric, different annealing steps were evaluated, and an activation anneal at only 700°C was found to yield the best results. Furthermore, we also investigated the temperature behavior of the tunnel FETs. Ideal tunnel FET behavior was observed for devices having ohmic Ni/Au contacts, and we demonstrate the invariance of both the SS and on-current with temperature, as expected for true tunnel FETs.