DocumentCode :
1290536
Title :
Hybrid partitioned H.264 full high definition decoder on embedded quad-core
Author :
Kim, Minsoo ; Song, Joon Ho ; Kim, Do-Hyung ; Lee, Shihwa
Volume :
58
Issue :
3
fYear :
2012
fDate :
8/1/2012 12:00:00 AM
Firstpage :
1038
Lastpage :
1044
Abstract :
In this paper, the problem of efficient mapping of the H.264 decoder on an embedded quad-core platform is addressed. For this purpose, a new partitioning method called `hybrid partitioning´ is proposed. Partitioning is a very important issue for the mapping of application software on multi-core systems. For H.264 video decoders, functional partitioning and data partitioning were proposed, and usually used. Hybrid partitioning is the mixture of two partitioning methods, and each module is partitioned by functional partitioning or data partitioning, depending on the module´s features. Compared with dedicated functional or data partitioning, hybrid partitioning is as powerful as data partitioning for load balancing between cores, and is also as efficient as functional partitioning from the viewpoint of memory requirement. Hybrid partitioning is also free from the macroblock level dependency problem that data partitioning usually has in video decoding. As a result of applying hybrid partitioning, 86.0% of waiting overhead is reduced, compared with functional partitioning. Regarding memory usage, hybrid partitioning requires 51.2% less VLIW (Very Long Instruction Word) program memory, and 62.0% less CGRA (Coarse-Grained Reconfigurable Array) program memory, than data partitioning. As for SDRAM (Synchronous Dynamic Random-Access Memory) bandwidth, compared with data partitioning, hybrid partitioning conserves the SDRAM bandwidth of 38.6MHz. This is 11.6% of the whole bandwidth budget of 333MHz SDRAM memory used in experiments. A parallelized decoder with hybrid partitioning on an embedded quad-core system is 3.5 times faster than that on a single core.
Keywords :
DRAM chips; SRAM chips; decoding; embedded systems; multiprocessing systems; resource allocation; video coding; CGRA program memory; H.264 video decoders; SDRAM; VLIW program memory; application software mapping; bandwidth 333 MHz; bandwidth 38.6 MHz; coarse-grained reconfigurable array program memory; data partitioning method; embedded quad-core system platform; functional partitioning method; hybrid partitioned H.264 full high definition decoder; hybrid partitioning method; load balancing; macroblock level dependency problem; multicore systems; parallelized decoder; synchronous dynamic random-access memory bandwidth; very long instruction word program memory; Bandwidth; Decoding; Load management; Memory management; Motion compensation; SDRAM; VLIW; H.264; Multi-core; data partitioning; functional partitioning; hybrid partitioning;
fLanguage :
English
Journal_Title :
Consumer Electronics, IEEE Transactions on
Publisher :
ieee
ISSN :
0098-3063
Type :
jour
DOI :
10.1109/TCE.2012.6311353
Filename :
6311353
Link To Document :
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