A new five-parameter MOS transistor mismatch model

Author

Serrano-Gotarredona, Teresa ; Linares-Barranco, Bernabé

Author_Institution

Nat. Microelectron. Centre, Seville, Spain

Volume

21

Issue

1

fYear

2000

Firstpage

37

Lastpage

39

Abstract

A new five-parameter MOS transistor mismatch model is introduced capable of predicting transistor mismatch with very high accuracy for ohmic and saturation regions, including short-channel transistors. The new model is based on splitting the contribution of the mobility degradation parameter mismatch /spl Delta//spl theta/ into two components, and modulating them as the transistor transitions from ohmic to saturation regions. The model is tested for a wide range of transistor sizes (30), and shows excellent precision, never reported before for such a wide range of transistor sizes, including short-channel transistors.

Keywords

CMOS analogue integrated circuits; MOSFET; carrier mobility; integrated circuit design; semiconductor device models; CMOS process; MOS transistor; analog VLSI design; five-parameter mismatch model; mobility degradation parameter mismatch; ohmic region; saturation region; short-channel transistors; transistor mismatch; transistor size; Analog circuits; Circuit simulation; Circuit testing; Degradation; Length measurement; MOSFETs; Microelectronics; Predictive models; Size measurement; Very large scale integration;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.817445

Filename

817445