Title :
Highly accurate SPICE-compatible modeling for single- and double-gate GNRFETs with studies on technology scaling
Author :
Gholipour, Morteza ; Ying-Yu Chen ; Sangai, Amit ; Deming Chen
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
Abstract :
In this paper, we present a highly accurate closed-form compact model for Schottky-Barrier-type Graphene Nano-Ribbon Field-Effect Transistors (SB-GNRFETs). This is a physics-based analytical model for the current-voltage (I-V) characteristics of SB-GNRFETs. We carry out accurate approximations of Schottky barrier tunneling, channel charge and current, which provide improved accuracy while maintaining compactness. This SPICE-compatible compact model surpasses the existing model [15] in accuracy, and enables efficient circuit-level simulations of futuristic GNRFET-based circuits. The proposed model considers various design parameters and process variation effects, including graphene-specific edge roughness, which allows complete and thorough exploration and evaluation of SB-GNRFET circuits. We are able to model both single- and double-gate SB-GNRFETs, so we can evaluate and compare these two types of SB-GNRFET. We also compare circuit-level performance of SB-GNRFETs with multi-gate (MG) Si-CMOS for a scalability study in future generation technology. Our circuit simulations indicate that SB-GNRFET has an energy-delay product (EDP) advantage over Si-CMOS; the EDP of the ideal SB-GNRFET (assuming no process variation) is ~1.3% of that of Si-CMOS, while the EDP of the non-ideal case with process variation is 136% of that of Si-CMOS. Finally, we study technology scaling with SB-GNRFET and MG Si-CMOS. We show that the EDP of ideal (non-ideal) SB-GNRFET is ~0.88% (54%) EDP of that of Si-CMOS as the technology nodes scales down to 7 nm.
Keywords :
CMOS integrated circuits; SPICE; Schottky barriers; elemental semiconductors; field effect transistors; graphene; silicon; tunnelling; CMOS; GNRFET; SPICE; Schottky barrier tunneling; Schottky-barrier-type graphene nano-ribbon field-effect transistors; Si; circuit simulations; circuit-level simulations; closed-form compact model; current-voltage (I-V) characteristics; energy-delay product; graphene-specific edge roughness; physics-based analytical model; size 7 nm; technology scaling; Approximation methods; Delays; Integrated circuit modeling; Logic gates; Schottky barriers; Transistors; Tunneling;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014
Conference_Location :
Dresden
DOI :
10.7873/DATE.2014.133