Title :
An Area-Efficient Multistage 3.0- to 8.5-GHz CMOS UWB LNA Using Tunable Active Inductors
Author :
Reja, M.M. ; Moez, Kambiz ; Filanovsky, Igor
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Alberta, Edmonton, AB, Canada
Abstract :
An area-efficient multistage 3.0- to 8.5-GHz ultrawideband low-noise amplifier (LNA) utilizing tunable active inductors (AIs) is presented. The AI includes a negative impedance circuit (NIC) consisting of a pair of cross-coupled NMOS transistors and is tuned to vary the gain and bandwidth (BW) of the amplifier. Fabricated in a 90-nm digital CMOS process, the proposed fully on-chip LNA occupies a core chip area of only 0.022 mm2. The measurement results show a power gain S21 of 16.0 dB, a noise figure of 3.1-4.4 dB, and an input return loss S11 of less than -10.5 dB over the 3-dB BW of 3.0-8.5 GHz. Tuning the AIs allows one to increase the gain above 18.0 dB and to extend the BW over 9.4 GHz. The LNA consumes 16.0 mW from a power supply of 1.2 V.
Keywords :
CMOS digital integrated circuits; MMIC amplifiers; active networks; inductors; low noise amplifiers; ultra wideband technology; CMOS UWB LNA; area-efficient multistage tunable active inductors; bandwidth 3.0 GHz to 8.5 GHz; cross-coupled NMOS transistors; digital CMOS process; gain 16.0 dB; input return loss; negative impedance circuit; noise figure 3.1 dB to 4.4 dB; power 16.0 mW; power gain; size 90 nm; ultrawideband low-noise amplifier; voltage 1.2 V; Artificial intelligence; CMOS integrated circuits; Capacitance; Gain; Noise; Radio frequency; Transistors; Active inductor (AI); CMOS; low-noise amplifier (LNA); shunt peaking; ultrawideband (UWB);
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2010.2055990
