DocumentCode
129111
Title
Optimal dimensioning of active cell balancing architectures
Author
Narayanaswamy, Swaminathan ; Steinhorst, Sebastian ; Lukasiewycz, Martin ; Kauer, Matthias ; Chakraborty, Shiladri
Author_Institution
TUM CREATE, Singapore, Singapore
fYear
2014
fDate
24-28 March 2014
Firstpage
1
Lastpage
6
Abstract
This paper presents an approach to optimal dimensioning of active cell balancing architectures, which are of increasing relevance in Electrical Energy Storages (EESs) for Electric Vehicles (EVs) or stationary applications such as smart grids. Active cell balancing equalizes the state of charge of cells within a battery pack via charge transfers, increasing the effective capacity and lifetime. While optimization approaches have been introduced into the design process of several aspects of EESs, active cell balancing architectures have, until now, not been systematically optimized in terms of their components. Therefore, this paper analyzes existing architectures to develop design metrics for energy dissipation, installation volume, and balancing current. Based on these design metrics, a methodology to efficiently obtain Pareto-optimal configurations for a wide range of inductors and transistors at different balancing currents is developed. Our methodology is then applied to a case study, optimizing two state-of-the-art architectures using realistic balancing algorithms. The results give evidence of the applicability of systematic optimization in the domain of cell balancing, leading to higher energy efficiencies with minimized installation space.
Keywords
Pareto optimisation; battery management systems; battery powered vehicles; energy storage; EESs; EVs; Pareto-optimal configurations; active cell balancing architectures; balancing currents; battery pack; charge transfers; electric vehicles; electrical energy storages; energy dissipation; inductors; installation volume; optimal dimensioning; optimization approaches; realistic balancing algorithms; smart grids; stationary applications; transistors; Charge transfer; Computer architecture; Energy dissipation; Inductors; MOSFET; Microprocessors; Pulse width modulation;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014
Conference_Location
Dresden
Type
conf
DOI
10.7873/DATE.2014.153
Filename
6800354
Link To Document