Title :
On GPU bus power reduction with 3D IC technologies
Author :
Young-Joon Lee ; Sung Kyu Lim
Author_Institution :
Sch. of ECE, Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
The complex buses consume significant power in graphics processing units (GPUs). In this paper, we demonstrate how the power consumption of buses in GPUs can be reduced with 3D IC technologies. Based on layout simulations, we found that partitioning and floorplanning of 3D ICs affect the power benefit amount, as well as the technology setup, target clock frequency, and circuit switching activity. For 3D IC technologies using two dies, we achieved the total power reductions of up to 21.5% over a baseline 2D design.
Keywords :
clocks; graphics processing units; integrated circuit layout; low-power electronics; three-dimensional integrated circuits; 3D IC floorplanning; 3D IC partitioning; 3D IC technologies; GPU bus power reduction; baseline 2D design; circuit switching activity; graphics processing units; layout simulations; power consumption; target clock frequency; technology setup; Bonding; Clocks; Graphics processing units; Integrated circuits; Layout; Radio frequency; Three-dimensional displays;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014
Conference_Location :
Dresden
DOI :
10.7873/DATE.2014.188
